The present invention relates to a method for sorting vector data and a vector processor suitable thereto.
When nonnumeric processing such as sorting or merging is performed by a scalar processor, the processing speed is low. In order to improve the processing speed, a method for performing nonnumeric processing such as sorting by a vector processor has been used and a vector processor therefor has been described in U.S. patent application Ser. No. 06/685,116 (filed on Dec. 21, 1984), now U.S. Pat. No. 4,779,192, assigned to the assignee of the present invention. As such a vector processor, an "integrated database processor of M 680H computer" is marketed by the present assignee.
In the above U.S. Patent Application and the above "integrated database processor", vector instructions exclusively used for sorting and a circuit for sorting vector data driven by the vector instructions are utilized. On the other hand, in the technique described in a Technical Report of the Institute of Electronics, Information and Communication Engineers of Japan, COMP 86-88 (pp. 79-85), a conventional numeric processing vector processor and basic vector instructions prepared therefor, for example, a move vector instruction and a plurality of vector operation instructions for arithmetic or logical operations are utilized.
In general, the vector processor enhances the processing speed by continuously processing a plurality of vector elements (vector processing) by means of a pipeline operated circuit. In order to enhance the processing speed, it is desirable to use a separate circuit for exclusively performing each one of different vector processings.
In this sense, the above "integrated database processor" is suitable for high speed processing of a sort operation.
However, in this processor, the sorting by the vector processor cannot be performed unless the data length of each element of vector data to be sorted is constant as determined by the particular computer.
For example, in the above "integrated database processor", the data length of the vector elements of the vector data to be sorted must be 4-byte length or 12-byte length.
However, where the data to be sorted are names of places, they may have longer data lengths than the above constant length. For those data, the above "integrated vector processor" performs the sort not by vector processing but by scalar processing. As a result, the processing speed is low.
Accordingly, it is desired to have a sort method for sorting by vector processing data longer than the constant data length given as the data length sortable by the vector processor, and a vector processor suitable thereto.
A technique for performing vector processing for a group of symbolic data trains is disclosed in U.S. patent application Ser. No. 06/737,686 (filed on May 24, 1985), now U.S. Pat. No. 4,723,206, assigned to the present assignee. In the technique of that application, vector data having symbolic trains of a constant length as elements are generated from the group of symbolic data trains, and each group of vector elements which are to belong to the same symbolic data train is processed as a partial vector. One more vector data for representing a punctuation between the partial vectors is used. This technique specifically discloses a method for searching by vector processing a symbolic train which matches a particular symbolic train from the group of symbolic data trains, as an example of the vector processing. However, this technique does not disclose a sort method. Further, it does not disclose a method for sorting by vector processing the group of symbolic trains having longer data lengths than the data length determined by the vector processor.